SB-USB2 - Logic Analyzer
Description of logic analyzer module

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Introduction
Capabilities
Example
Configuration

Introduction

The logic analyzer module is available only for SB-USB2 and SB-USB2-ZSP.

Logic analyzer window and controls

Part of the SB-USB2 JTAG emulator is 40 MHz logic analyzer module. It allows monitoring of any of the target system signals, and for advanced triggering of the target processor. The external connector has 24 pins, with some of them dedicated for the JTAG control, but rest can be used for signal monitoring and control. Emulator can be configured in several pinout modes, allowing matching default emulation headers from following manufacturers: Freescale DSP56K (OnCE and JTAG), VeriSilicon ZSP, Actel A3P. The unused signals can be used as inputs to logic analyzer, and also as configurable control signals.

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Capabilities

The logic inside the SB-USB2's FPGA allows capturing up to 2048 24-bit samples. The sampling can occur on any sampling frequency divided from the maximum of 40 MHz. The programmable divider 24-bit counter allows setting the sampling frequency down below 1 Hz if needed. Up to 24 input signals can be used to configure 4 independent triggers, with 3 states: high, low and don't care.
Two 24-bit programmable counters, which could be used in the logic trigger configuration.
Eight level sequencer allows building complex trigger conditions.
The data capturing can be delayed by any number of cycles between 0 and 2047 - this allows setting the display window at any position around the "completed" condition.
When the trigger occurs, it can be used to stop the target processor, with debug request signal. For legacy OnCE interface (DSP56002) it is -DR signal, for current Freescale DSP devices (DSP563xx) this is -DE. For devices not equipped with the -DE signal, one of the external interrupts can be used, but this will require some programming on the DSP side.
The distance between any two locations on the display can be measured by way of two cursors. Secondary cursor is activated with the Shift key. Cursors could be moved to the next edge with Ctrl-Left/Right keys. The display window can be zoomed in with Ctrl-PgUp/PgDn keys.

Any of the signals can be used also as digital output controlled by the PIN command. For description please review SB-USB2 Custom Resets

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Example

Logic analyzer window and controls

In the above example the host port of the DSP56311 is monitored. The trigger 1 is set to host data read from host port address 7. On the trigger event the -DE signal is sent to the target processor, causing it to stop in the debug mode. Two graphic cursors are used to measure the width of the read strobe, which is 240 ns.

Connections between SB-USB2 and target board

The above picture illustrates interconnections between SB-USB2 and a target board. Individual wires are connected from the QUAD-JTAG-DA adapter. Inside the emulator, all pins are connected to the logic, except of the pin #4 providing ground reference. The Host Port Interface of the DSP56311EVM is accessed through the USB-EVM-C adapter.

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Configuration

Logic analyzer trigger configuration

Any of the 24 emulator's pins can be used as a trigger. Some signals are reserved for the JTAG operation, but if the JTAG is not used, and there is external ground provided all 24 signals are available. For normal emulator operation with JTAG interface of Freescale DSP following signals are reserved:

  • 1 - TDI
  • 3 - TDO
  • 5 - TCK
  • 10 - TMS
  • 4 - Gnd

Stop delay defines number of cycles to continue samples collection after Stop condition occurred.
Sampling Clock defines counter value used to divide 40 MHz input clock
Samples field shows current position of the pointer in the capture buffer, and current state of logic analyzer flags including triggers, capture complete and operating mode.
Counter1/2 allows setting the reload value for counters, and also shows current value of the counter.
Seq shows current level of the sequencer
Stop DSP check box for the target debug request
Auto start check box for automatically rearming logic after the Stop condition
Trace Control conditions used for Starting, Pausing, Stopping, Resetting and counting of the counters

Logic analyzer sequencer configuration

This dialog allows setting events for advancing or resetting of the sequencer state machine.

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