SB-USB2 - User Pins
Custom resets and I/O pins

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The custom resets and individual pin control is available only for SB-USB2 and SB-USB2-ZSP. This feature requires sbusbd32.dll version 1.10.47 (or later) and SB-USB2 FPGA logic version 1.44 (or later)

The JTAG interface used for debugging in most cases does not allow for device reset. This can be implemented as a special JTAG command, but if it is not, most of the JTAG emulators provide additional signal, which could be used to reset the target processor. In case of muli-processor targets connected on the single JTAG scan chain, reset of one device will cause sending reset signal to all other ones.
SB-USB2 has total of 24-pins, with 5-7 pins dedicated for the JTAG operation: Gnd, TDI, TDO, TCK, TMS, (TRST, -DE). It means that remaining 17 signals could be used for Logic Analyzer operation or for custom signals sent to target.

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The first 14 signals of the SB-USB2 are connected through the primary 14-pin IDC socket. The typical pinouts for Freescale DSP56K and VeriSilicon ZSP are shown below. The SB-USB2 can be also configured in the ARM and in the Actel JTAG pinout mode.

Typical DSP56K pinout
 TDI |1   2|(GND)
 TDO |3   4| GND
 TCK |5   6|(GND)
  nc |7   8| key
 RST |9  10| TMS
 Vcc |11 12|(TMS2)
 -DE |13 14|-TRST

Typical ZSP pinout
TRST |1   2|(GND)
 TDI |3   4| GND
 TDO |5   6|(GND)
 TMS |7   8|(GND)
 TCK |9  10|(GND)
 EVT |11 12| OPT1
-RST |13 14| OPT2

The secondary connector provides additional 10 signals, which can be used for any purpose.

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To functionally tie any of the user pins to the debugger's RESET command "SET RESETPIN n" can be used. This needs to be done for each target device during the debugger initialization. The reset pin can be also assigned by the environemnt variable set in the operating system:
The 'x' represents the physical device sequence on the JTAG scan chain, where the device #0 is closest to the TDO. The 'y' represents emulator's pin number to be used for the reset function for the selected device. This can be a number between 1 and 24, but most likely those will be signals from the secondary connector (15..24). For the DSP56K the RESET command executes few operation on the emulator's driver level. After -RESET signal is asserted, there is a DR (debug request) command sent over the JTAG. When the -RESET is deasserted and tristated, DSP device should be stopped at the entry into the bootstrap routine (0xFF0000).

To activate any of the other unused pins for the custom target control debugger supports PIN command. In the default state unused pins are tristated (set as inputs for logic analyzer). The PIN command allows to set any pin state to low, high or HiZ. The PIN will not affect any of the dedicated JTAG signals. JTAG signal fuctionality is resolved on higher logic level then the custom pin settings.
The syntax for the PIN command is as follows:
PIN [?|x [y]]

If there is no parameter provided, it will display current PIN settings. The results will be stored into the system variables, so the command file could use it for flow control:
V100 - current input values
V101 - selected output enable
V101 - selected output level

If there is only pin number provided, the results will be stored as follows:
V100 - current pin value (0 or 1)
V101 - selected output mode (0, 1 or 2 for HiZ)

If the second parameter is specified, it will be interpreted as pin mode: 0, 1 or 2 for HiZ.

The parameters for the pin command can be passed through system variables, so sequence of pin changes can be generated from the command script.

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