SB-USB2-ZSP
JTAG Emulator for ZSP Cores

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Brochure: sb-usb2-zsp_br.pdf (731 KB)
User Guide:
sb-usb2-zsp_ug.pdf (965 KB)


The SB-USB2-ZSP emulator enables efficient and productive embedded software debugging. This compact an portable probe utilizes the JTAG interfaces for debug and in-circuit testing supplied with the ZSP cores with upload and download rates up to 5 times faster than comparable products. It integrates well with both ZSP SDK debuggers and ZViewIDE, allowing for the maximum amount of flexibility in choosing a debugging front-end.

Features

Description

Transfer Rate

Ordering


 

Features

SB-USB2-ZSP:

  • Powered by USB port
  • JTAG interface
  • Logic Levels: 3.3V, 2.5V, 1.8V
  • TCK: 8 kHz - 10 MHz
  • Execution Time Measurement
  • Logic anlyzer

Integrates with:

  • ZViewIDE
  • ZSP-ARM Development System

When used with Verisilicon's ZViewIDE development environment, the SB-USB2-ZSP supports multi-core and multi-user debugging on a network over a TCP/IP connection and flash memory programming. It supports accurate measurement of execution time with a 27 nanosecond resolution in Hardware mode and a 5 microsecond resolution when in Software mode benchmarking.

The emulator supports unlimited software breakpoints within all ranges of program memory implemented in RAM.

The SB-USB2-ZSP is the emulator used by the ZSP/ARM development system, which provides a powerful interface to embedded project development from CPU evaluation to production testing This multi-core development environment provides a debug interface running on a PC host connected to the fast SB-USB2-ZSP emulator, which communicates with the ZSP/ARM targets.

You can use the SB-USB2-ZSP emulator to program external flash memory devices in the lab or on the production/test floor using simple command files.  Review  zspflash for more details.

SB-USB2 features integrated 40 MHz Logic Analyzer. This feature allows for signal monitoring and advanced trigerring. Any of the not used emulator's pins can be used also as an output. Please refer to SB-USB2 Custom Resets.

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Description

The JTAG interface can be configured to operate with logic levels of 3.3V, 2.5V, or 1.8V. The JTAG clock can be configured between 32kHz and 10MHz.

The SB-USB2-ZSP probe is powered by the USB connection, making it ideal for use by notebook computers or lab environments. Take advantage of our  Emu-Test utility (free) to verify your JTAG connections.

a flexible ribbon cable provides the JTAG interface featuring both a primary and secondary connector:

         Primary Connector:

     +-----+
TRST |1   2| GND
 TDI |3   4| GND
 TDO |5   6| GND
 TMS |7   8| GND
 TCK |9  10| GND
     +-----+

The optional secondary connector provides an extra control signal which can be used to reset the target. This pin is active low, and when not in use it is tri-stated; thus, it has no effect on the operation of the target circuitry. Execution of the zspusbreset program from a DOS prompt will assert a reset signal on the target ZSP. a command line parameter allows to customize length of the reset pulse.

         Secondary Connector:

     +-----+
TRST |1   2| GND
 TDI |3   4| GND
 TDO |5   6| GND
 TMS |7   8| GND
 TCK |9  10| GND
 EVT |11 12| OPT1
-RST |13 14| OPT2
     +-----+
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File I/O Transfer Rate

The following comparison illustrates the execution of a fwrite function on the ZSP 402ZX, the data transfer data rate depends on the size of the data block being transfered. Transfer data rate was calculated by repeat executiion of the fwrite function for 10 seconds.

Tests were done on the DT402EB board, with monitor code executed out of the internal memory, on WindowsXP/P4-3GHz computer.

 

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